Modern semiconductor packages are formed from multiple layers that may include numerous active components electrically coupled together by metal conductor interconnects. Although aluminum conductors with silicon dioxide disposed between such interconnects have been used in the past, current practices in fabricating high speed semiconductor devices and have moved toward using a combination of copper interconnects with suitable dielectric materials or films such as low-k dielectrics to take advantage of the superior conductivity of copper compared to aluminum and reduced parasitic capacitance between the conductors.
Back end-of-line (“BEOL”) processes are used to create the intricate network of conductor interconnects in each layer and between the multiple layers wherein copper is laid into the dielectric material. An additive patterning process referred to as “dual damascene” is one BEOL process used to form the patterned copper conductor circuit(s) which interconnect various active components (e.g., resistors, transistors, etc.) disposed in the single and multiple layers throughout the microchip. Some of these interconnect circuit structures include trenches which are filled with the copper conductor and vias which are essentially metal-plated or filled holes that electrically connect the conductors between the layers in the semiconductor packages.
These open trench and via structures are formed in the dielectric material using various processes such as dry gas plasma etching. Dry etching is performed in an etcher machine by applying an electromagnetic energy source (such as RF) to a gas containing a suitable chemically reactive element that reacts with the material to be etched or removed. The gas plasma emits positively charged ions that strike and dissolve the dielectric material. By placing hard masks above the dielectric material layer with openings configured in the shape of the circuit desired to be formed, various patterns of trench and via openings can be made in the dielectric material since dielectric material beneath the hard mask will not dissolve. Because the ions strike the dielectric material essentially perpendicular to its surface, vertical trench and via profiles can be created with virtually no undercutting beneath the hard mask.
After the trenches and vias are formed by dry etching, copper may be deposited in these open structures in the dielectric by any suitable known technique such as chemical vapor deposition (CVD), physical vapor deposition (PVD), electro-chemical plating (ECP), electroless-plating, etc. Subsequent processes such as chemical mechanical planarization (CMP) or etching may be used in some instances as needed to polish and plane the top surface of the dielectric material layer, thereby leaving an essentially flat surface on which subsequent layers of dielectric with interconnects can be built.
Referring to FIG. 1, a conventional known BEOL dual damascene process is shown in sequential steps as indicated by the process directional arrows. The semiconductor package consists of a bottom etch stop layer, a dielectric layer formed thereon, a dielectric anti-reflective coating (DARC) formed thereon to protect the dielectric layer during photolithography and photoresist ashing, and a patterned photoresist layer (PR) formed thereon having a via profile. As shown in FIG. 1, this conventional dual-damascene BEOL process requires at least two hard masks for separately forming vias and trenches in the semiconductor layer. Because a separate via mask and trench mask are typically needed, the separate trench and via formation in the semiconductor layer under these circumstances must be completed in two dry etcher chambers (see Etcher Chambers #1 and 3). The via is fully formed in the semiconductor layer in Etcher Chamber #1, typically by dry plasma gas etching. After formation of the via, the exposed bottom etch stop layer at the lower end of the via is protected with a photoresist plug coating to prevent the bottom layer from being opened when the trenches are subsequently etched into the dielectric material in Etcher Chamber #3. This requires another operation called plug etch back (PEB) after the trench is formed in yet a third Etcher Chamber #2 to remove the plug material from top surface of the DARC so that a second patterned photoresist layer having a trench profile can be added thereon. The second patterned photoresist layer is then used to fully form the trench in the semiconductor layer. Accordingly, the via and trenches are formed in separate etcher chambers.
Consequently, in order to complete the foregoing steps in a conventional semiconductor BEOL process, at least three dry etcher chambers have been used to complete the separate etching steps of forming vias, forming trenches, and PEB. This monopolizes available etcher chamber capacity and results in a complex fabrication process that is time consuming and expensive. According, semiconductor package fabrication costs are increased while the number of wafers per hour that can be processed is reduced.
An improved semiconductor dual damascene method is desired.